1. Field of the Invention
This invention relates to a method for chemically polishing a semiconductor substrate using a polishing turn table to thereby flatten the same, and also to an apparatus for executing the method.
2. Description of the Related Art
In general, semiconductor devices such as ICs, LSIs, etc. are formed in the following processes: A design process for designing an integrated circuit to be formed on a semiconductor substrate; a mask-forming process for patterning the substrate with an electron beam to form the integrated circuit; a wafer-forming process for forming a wafer of a predetermined thickness from a monocrystalline ingot; a water-treating process for forming a semiconductor element such as an integrated circuit on the wafer; and an assembling/inspecting process for dividing the wafer into semiconductor chips and packaging them into semiconductor devices. Each process requires an apparatus dedicated thereto. In addition to the apparatus dedicated to each process, apparatuses necessary for the overall equipments and the environment, such as a pre-treatment apparatus, an exhaust-gas treatment apparatus, etc., are used to manufacture semiconductor devices.
In the conventional wafer treatment process, a CMP (Chemical-Mechanical Polishing) method is used to flatten the surface of a semiconductor substrate, which is obtained after any voluntary films such as a metal film, a polysilicon film, a silicon oxide film (SiO.sub.2) film, etc. are embedded in trenches or contact holes formed therein.
FIG. 1 is a schematic sectional view, showing a general CMP apparatus for flattening a wafer surface. As is shown in FIG. 1, a turn table 16, which includes a polishing disc 17 and a support unit 15, is placed on a stage 11 with a bearing 13 interposed therebetween. A polishing pad 19 is attached to the upper surface of the polishing disc 17 for polishing a wafer. A driving shaft 21 is provided for rotating the turn table 16. The driving shaft 21 is rotated by a motor 23 via a rotating belt 25. On the other hand, a semiconductor wafer 20 is supported by a wafer carrier 33. The wafer carrier 33 has a retainer ring 29 and an adsorption pad 31 for holding the wafer by a vacuum force or the tension of water. The wafer 20 has its position controlled by the wafer carrier 33 such that it is opposed to the polishing pad 19. The wafer carrier 33 is connected to a driving shaft 35. The driving shaft 35 is rotated by a motor 37 via gears 39 and 41, and fixed to a driving unit 43 for vertically move the shaft 35.
In the above-described structure, the driving unit 43 vertically moves in accordance with vertical movement of a cylinder 45, thereby moving the wafer 20 attached to the wafer carrier 33 to or from the polishing pad 19. At the time of polishing, an appropriate polishing slurry is supplied between the wafer 20 and the polishing pad 19. Further, the wafer 20 can be horizontally moved during polishing by means of another driving unit (not shown).
Referring then to FIGS. 2A and 2B, an example of a flattening treatment of a wafer surface by the FIG. 1 CMP apparatus using the CMP method will be described. First, an Si.sub.3 N.sub.4 film 7 is formed on a semiconductor substrate 1. Then, the film 7 and the substrate 1 is patterned by etching to form grooves 8. An SiO.sub.2 film 5 is deposited on the film 7 and in the grooves 8 (see FIG. 2A).
Thereafter, the SiO.sub.2 film 5 is polished by the CMP method until the Si.sub.3 N.sub.4 film 7 which will serve as a stopper film is exposed. As a result, the embedding of the SiO.sub.2 film 5 into the grooves 8 is completed, and at the same time the surface of the semiconductor substrate 1 is uniformly flattened (see FIG. 2B).
It should be noted that the CMP method itself is not a new technique but a conventional one used in the aforementioned wafer-forming process.
This CMP technique has recently been used in a process for manufacturing a highly integrated semiconductor device.
Referring then to FIGS. 3A, 3B and 4A to 4C, applications of the CMP technique will be described.
FIGS. 3A and 3B show an application of the CMP method used in a process for separating trench elements. After an SiO.sub.2 film 2 is formed by thermal oxidation of the surface of the semiconductor substrate 1, an Si.sub.3 N.sub.4 film 7 which will serve as a stopper film is formed by the CVD method. Subsequently, the films 2 and 7 are patterned by lithography to form grooves 9. Those surface portions of the semiconductor substrate 1 which constitute the inner surfaces of the grooves 9 are oxidized, and then boron is injected into the bottoms of the grooves 9 to form channel cut regions 10. Thereafter, a polysilicon film 3 is formed by the CVD method on the Si.sub.3 N.sub.4 film 7 and in the grooves 9 (FIG. 3A). An SiO.sub.2 film may be used in place of the polysilicon film. Then, the polysilicon film 3 on the semiconductor substrate 1 is polished until the Si.sub.3 N.sub.4 film 7 is exposed (FIG. 3B). In this case, a polishing rate as low as about 1/10-1/200 is employed, and hence the polishing can be stopped when the Si.sub.3 N.sub.4 film 7 is exposed. Thus, the polysilicon film 3 is formed only in the grooves 9. As is evident from the above, the polishing can be stopped just when the stopper film is exposed, by using, as the stopper film, a film of a polishing rate lower than that of a film to be polished, and designating an appropriate polishing period of time.
Referring to FIGS. 4A to 4C, an application of the CMP method used to embed a metal wire in a groove formed in an insulating film will be described.
A CVD-SiO.sub.2 film 5 and a plasma SiO.sub.2 film 12 are sequentially formed on the semiconductor substrate 1. Then, the plasma SiO.sub.2 film 12 is patterned to form grooves 14 therein. A Cu film 16 is deposited in the grooves 14 and on the film 12 (FIG. 4A). The Cu film 16 is polished using the plasma film 12 as a stopper film. When the plasma film 12 has been exposed, the polishing of the Cu film 16 is finished, thereby finishing the embedding of the Cu film 16 in the grooves 14. Thus, an embedded Cu wire is formed (FIG. 4B). As a result of polishing, the surface of the semiconductor substrate 1 is flattened, which facilitates forming of a plasma SiO.sub.2 film 18 as a second layer on the substrate (FIG. 4C). The flattening by the CMP method facilitates forming of electrode wires (not shown) as second and third wire layers.
At the time of polishing a polysilicon film or an oxide film formed on a semiconductor wafer using the conventional CMP apparatus, a colloidal silica polishing slurry, which is made by mixing silica particles as polishing particles with an alkaline solvent, is supplied to the working area of the polishing pad (which is brought into contact with the semiconductor wafer). The reason why the alkaline polishing slurry is used is that polysilicon reacts to hydroxide ions, which accelerates polishing. In light of this, NaOH, KOH, NH.sub.3, etc. is added into a solvent. This will inevitably produce a great amount of metal impurities as compared with the other processes, and will cause contamination.
On the other hand, at the time of polishing a 10 metal film formed on a semiconductor wafer, a polishing slurry made by mixing polishing particles with an acidic solvent is supplied to the working area. The reason why the acidic polishing slurry is used is that the metal film reacts to hydrogen ions, which accelerates polishing. Since an additive for making the polishing particles acidic contains metal impurities such as iron, etc., a great amount of metal impurities will be produced as compared with the other processes, and hence contamination may well occur.
To avoid such contamination, it is necessary to perform chemical cleaning at least twice, i.e. after polishing and before the next treatment, which will inevitably make the manufacturing process complicated and increases the cost of the equipments.